 |
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
| Datasheet File OCR Text: |
| IBM39STB032XX IBM39STB034xx Preliminary STB032xx and STB034xx Digital Set-Top Box Integrated Controllers Features Overall * High-End Set-Top Box technology * Four major subsystems integrated with IBM(R) on-chip CoreConnectTM structure. * Maximum MIPS for OS and application tasks * Simplified driver and software development * Scalable, flexible, and extendible * 108 MHz/150 MIPS and 162 MHz/225 MIPS versions available * 3.3 V and 2.5 V power supplies * IBM CMOS SA-12E (0.25 m) process technology * 304-pin PBGA package MPEG-2 Digital Audio/Video Subsystem * MPEG-2 Video Decoder * MPEG-2 Audio Decoder * MPEG-2 Transport/DVB Descrambler * Dolby(R) Digital Audio1 support on selected parts * Macrovision Copy Protection on selected parts * Display Controller * Digital Encoder (DENC) with six outputs * Anti-Flicker Filter PowerPC 405TM Host Processor: PPC405B3 CPU * 16KB Instruction, 8KB Data caches * Universal Interrupt Controller Memory Subsystem * DMA Controller * Cross-Bar Switch * External Bus Interface Unit (EBIU) * IDE interface * Two SDRAM Controllers Peripheral Subsystem * General Purpose Timers (GPTs) * Pulse Width Modulators * 1284 Parallel Port * Two Smart Card controllers * Two I2C Interfaces * 16550 Serial Communications Port * Infrared Serial Communications Port * General Purpose Input/Output (GPIO) * Serial Controller Port * Modem Serial Interface/Digital Audio Input Description IBM STB03xxx Digital Set-Top Box Integrated Controller family are highly integrated silicon devices specifically developed for digital set-top box (STB) applications using industry-leading IBM CMOS SA12E (0.25 m) process technology. The STB03xxx is part of the second generation of IBM products for digital STB applications. PowerPC processing and peripheral I/O architecture provide a high level of performance and functionality when used in audio and video subsystems. The resulting STB technology is full-functioned and easy to use. The STB03xxx minimizes host processor intervention to maximize MIPS for operating system and application tasks. Most of the features required in the back end of typical midrange and high-end STBs are integrated. Driver and software development is facilitated while preserving scaleability, flexibility, and extendibility. Architecturally, the devices consist of four subsystems interconnected and tuned using CoreConnect, the IBM multiple-bus, on-chip interconnect structure: 1. PowerPC host processor 2. Digital audio/video 3. Memory interface 4. Peripheral These high performance subsystems are suited to advanced interactive STBs with demanding software requirements including web browsers and JavaTM. 1. This implementation has not yet completed the evaluation process by Dolby Laboratories and is offered subject to obtaining approval. A Dolby Digital Audio license is required from Dolby Laboratories. STB03_sds_041800.fm.01 April 18, 2000 Features Page 1 of 55 IBM39STB032XX IBM39STB034xx STB032xx and STB034xx Digital Set-Top Box Integrated Controllers Preliminary Ordering Information Part Number IBM39STB03200PBB09C MPEG IBM39STB03201PBB09C 150 MIPS IBM39STB03210PBB09C IBM39STB03211PBB09C IBM39STB03400PBB06C MPEG IBM39STB03401PBB06C 225 MIPS IBM39STB03410PBB06C IBM39STB03411PBB06C 162 MHz MPEG/Dolby Digital1 None Macrovision2 108 MHz MPEG/Dolby Digital1 None Macrovision2 None Macrovision2 Performance (est.) Clock Speed Audio Copy Protection None Macrovision2 1. These parts include Dolby Digital enabling software and require the user to obtain a license from Dolby Laboratories Licensing Corporation. Please see "Dolby Digital Licensing" on page 3. 2. These parts support Macrovision Copy Protection and require that a license be in effect between the purchaser and Macrovision Corporation. Please see "Macrovision Licensing" on page 3. Conventions and Notation Throughout this document, standard IBM notation is used, meaning that bits and bytes are numbered in ascending order from left to right. Thus, for a 4-byte word, bit 0 is the most significant bit and bit 31 is the least significant bit. Overbars, e.g. TxEnb, designate signals that are active low. Numeric notation is as follows: Hexadecimal values are in single quotes and preceded by "x" or "X." For example: x'0B00'. Binary values are spelled out (zero and one) or appear in single quotes and preceded by a "b." For example: b`10101'. Settings of a bit or field are binary numbers but are often displayed in tabular form without quotes or the preceding "b." For example: 00 : 30 frames per second 01 : 15 frames per second 11 : 10 frames per second Ordering Information Page 2 of 55 STB03_sds_041800.fm.01 April 18, 2000 Preliminary IBM39STB032XX IBM39STB034xx STB032xx and STB034xx Digital Set-Top Box Integrated Controllers Licensing Requirements Dolby Digital Licensing Dolby Digital audio enabling software is provided with the IBM39STB0321x and IBM39STB0341x products. Dolby is a trademark of the Dolby Laboratories. Supply of this implementation of Dolby Technology does not convey a license or imply a right under any patent, or any other Industrial or Intellectual Property Right of Dolby Laboratories, to use this implementation in any end-user or ready-to-use final product. Companies planning to use this implementation in products must obtain a license from Dolby Laboratories Licensing Corporation before designing such products. Additional per-chip royalties may be required and are to be paid by the purchaser to Dolby Laboratories, Inc. Details of the OEM Dolby Digital license may be obtained by writing to: Dolby Laboratories Inc. Dolby Laboratories Licensing Corporation Attn: Intellectual Property Manager 100 Potrero Avenue San Francisco, CA 94103-4813 Macrovision Licensing Macrovision Copy Protection is supported in the IBM39STB032x1 and IBM39STB034x1 products. These devices are protected by U.S. patent numbers 4,631,603, 4,577,216, and 4,819,098 and other intellectual property rights. The use of Macrovision's Copy Protection technology in the device must be authorized by Macrovision and is intended for home and other limited pay-per-view uses only, unless otherwise authorized in writing by Macrovision. Reverse engineering or disassembly is prohibited. A valid Macrovision license must be in effect between the STB03xx1 purchaser and Macrovision Corporation. Additional per-chip royalties may be required and are to be paid by the purchaser to Macrovision Corporation. Macrovision Corporation 1341 Orleans Avenue Sunnyvale, CA 94089 STB03_sds_041800.fm.01 April 18, 2000 Licensing Requirements Page 3 of 55 IBM39STB032XX IBM39STB034xx STB032xx and STB034xx Digital Set-Top Box Integrated Controllers Preliminary Architecture and Subsystem Information Block Diagram Interrupts GPT PWM IEEE 1284 Smart Card0 Smart Card1 OPB Bus JTAG TRACE UIC PPC405B3 CPU 16K-I 8K-D Cache Cache EBIU OPB Bridge PLB0 Crossbar PLB1 SDRAM0 Controller SDRAM1 Controller DMA Controller SRAM IDE PER. DEVICE FLASH ROM SDRAM I C0 I2C1 Serial0/ 16550 Serial1/ Infrared 2 Transport DVB Descrambler SDRAM NIM Descrambler GPIO Serial Control Port Modem Interface Video Decoder OSD Digital Encoder DAC Ext Digital Encoder 2D/3D Graphics Audio Decoder Audio D/A IEC-60958 Architecture and Subsystem Information Page 4 of 55 STB03_sds_041800.fm.01 April 18, 2000 Preliminary IBM39STB032XX IBM39STB034xx STB032xx and STB034xx Digital Set-Top Box Integrated Controllers PowerPC 405B3 Host Processor Subsystem The PowerPC 405B3 (PPC405B3) subsystem handles all system initialization and control and also provides power and flexibility for product differentiation. PPC405B3 Subsystem PPC405B3 Processor CPU UIC Interrupt Controller Interface Timers: PIT, FIT, 64-bit base Multiplier/Divider Interrupts RISC Execution Unit Core Clocking Thirty-two 32-bit GPRs Clocks Power Mgmt DCRs JTAG (See Note) Interfaces MMU 16KB I-cache Array Instruction Cache Controls Data Cache Controls 8KB D-cache Array PLB Master PLB Master Note: The JTAG interface is used for development. PowerPC 405B3 CPU The PPC405B3 provides high performance and low power consumption. The CPU executes at sustained speeds of greater than one cycle per instruction at 108 or 162 MHz. Interrupt latency is three cycles, the best time for critical interrupts. STB03_sds_041800.fm.01 April 18, 2000 Architecture and Subsystem Information Page 5 of 55 IBM39STB032XX IBM39STB034xx STB032xx and STB034xx Digital Set-Top Box Integrated Controllers Preliminary On-chip instruction is compatible with PowerPC User Instruction Set Architecture, with branch prediction execution for most instructions. There are 32 x 32 bit general purpose registers. Instruction and data cache arrays improve system throughput. The CPU has a separate two-way set-associative 16KB instruction cache and an 8KB write-back/write-through data cache. Multiply and divide instructions are performed in hardware and are not emulated in software. Universal Interrupt Controller The Universal Interrupt Controller (UIC) provides all necessary control, status, and communication functions between all sources of interrupts and the PPC405B3. The UIC combines STB03xxx interrupts and presents them to the PPC405B3's critical or non-critical inputs. All interrupts can be programmed to generate either critical or non-critical output. Interrupts can be level- or edge-sensitive and interrupt polarity is programmable. An optional read-only vector is used to reduce critical interrupt servicing latency. This vector is generated by combining an offset (based on the bit position of the highest priority, enabled, and active critical interrupt) and a vector base address register. A configurable priority control bit determines whether the least significant or most significant bit in the status register has the highest priority. Clock and Power Management For power-saving purposes, a Clock and Power Management (CPM) input is used to shut down clocks and device functions. A reset is required to activate a unit. Memory Interface Subsystem The memory interface subsystem provides the system memory controller interface for SRAM, FLASH Memory, ROM, and SDRAM. It also provides the Direct Memory Access (DMA) interfaces for these memories. A key advantage of the memory interface is its ability to gain concurrent access (one function to SDRAM0 and one function to SDRAM1) and mutual access (a given function can access either port). Memory Subsystem DMA EBIU FLASH, ROM, etc. SDRAM PLB0 Crossbar EBIU SDRAM0 SDRAM SDRAM1 PLB1 Direct Memory Access Controller The four-channel DMA controller is a processor local bus master that allows faster data transfer between memory and peripherals than with program control. The controller supports memory-to-memory, peripheralto-memory, and memory-to-peripheral transfers. The DMA controller allows the PPC405B3 processor to execute instructions with no bus contention when the PPC405B3 is executing from cache. DMA is useful when Architecture and Subsystem Information STB03_sds_041800.fm.01 April 18, 2000 Page 6 of 55 Preliminary IBM39STB032XX IBM39STB034xx STB032xx and STB034xx Digital Set-Top Box Integrated Controllers the overhead associated with the controller setup is minimal compared to the time it would take to move data using program control load and store instructions. Each DMA channel has an independent set of registers for data transfer. The registers store data for control, source address, destination address, and transfer count. Each channel also supports chained DMA operations, therefore every channel also includes a chained count register in which case source address registers function as chained address registers. All DMA channels report their status to the DMA execution unit. The DMA controller also supports: * Internal DMA channels for 1284 parallel port, Smart Card interface, 16550 serial communications controller, infrared communications controller, etc. * 16- and 32-bit peripherals (on-chip peripheral bus and external) * 32-bit addressing * Address increment or decrement * Internal data buffering capability * Memory-mapped peripherals Processor Local Bus The Processor Local Bus (PLB) interfaces directly with the PPC405B3 and the other major subsystems (see "Block Diagram," on page 4). The STB03xxx uses three PLBs to provide high bandwidth between the function masters and the external memory interfaces for ROM, Flash, and SDRAM, etc. The STB03xxx PLB architecture includes a crossbar switch to present both memory interfaces as flat, shared memory spaces. External Bus Interface Unit The External Bus Interface Unit (EBIU) expands the local bus to transfer data between the PLB and a wide range of memory and peripheral devices attached to the external bus (see the following list). The EBIU can control up to eight devices or banks or regions of FLASH memory (128 MB), and a low latency maximizes system performance. The EBIU supports: * A direct connect SRAM/ROM/PIA interface for - up to eight SRAM/ROM/PIA banks with programmable address select - programmable or device-paced wait states - burst mode (BME) and single-cycle transfers * 16- and 32-bit byte addressable bus width * Programmable target word first or sequential cache line fills * IDE interface * supports ATA-3 Mode 4 register and PIO transfers * supports Mode 2 Multiword DMA transfers (see ANSI X3.298-1997, AT Attachment-3 Interface (ATA3)) * DVB Common Interface Support * External bus master with support for device master and master/slave * Common bank-specific programmability * Device-paced ready input STB03_sds_041800.fm.01 April 18, 2000 Architecture and Subsystem Information Page 7 of 55 IBM39STB032XX IBM39STB034xx STB032xx and STB034xx Digital Set-Top Box Integrated Controllers Preliminary SDRAM Controller The SDRAM Controller transfers data between the PLB and up to two SDRAM memory banks attached to the external bus. The Controller implements address and data pipelining and supports 16Mb and 64Mb SDRAMS concurrently. It also provides the following: * * * * * * Direct-connect SDRAM interface High bandwidth with a narrow 16-bit interface Page interleaving Programmable address select Programmable rates for automatic SDRAM refresh Software-initiated and self refresh modes for power savings Crossbar Switch The PLB Crossbar Switch (CBS) creates a flat memory model and implements Unified Memory Architecture (UMA), which connects multiple PLB master buses to multiple PLB slave buses, thus allowing two sets of PLB buses to intercommunicate. Processor, transport, and the audio and video decoders can access memory through either memory controller. Digital Audio/Video Subsystem The MPEG-2 Digital Audio/Video subsystem provides fully-synchronized playback of digital video and audio programs, with a minimum of interaction from the PPC405B3 processor. DVB Descrambler Audio PLL MPEG-2 Dolby Digital Audio Decoder NIM to Audio D/A and IEC60958 VCXO Auxiliary MPEG-2 Transport MPEG-2 Video Decoder OSD Auxiliary Port DENC PLB0 MPEG-2 Video Decoder with OSD The MPEG-2 video decoder provides decompression, decoding, and synchronized playback of digital video streams with a minimum of host support. It produces interlaced video output and can support MPEG-2 compressed data streams up to an average rate of 15 Mbps. The video decoder is also backward compatible to support the ISO/IEC International Standard 11172-2 (11/93) (also called "MPEG-1 Standard"). It supports the ISO/IEC 13818-2 Main Profile at Main Level. Architecture and Subsystem Information PLB1 Page 8 of 55 STB03_sds_041800.fm.01 April 18, 2000 Preliminary IBM39STB032XX IBM39STB034xx STB032xx and STB034xx Digital Set-Top Box Integrated Controllers The decoder also supports MPEG-2 MP@ML compliance with 2MB memory. Only 2MB of memory are needed to decode full CCIR601 resolution NTSC and PAL encoded MPEG-2 bitstreams. It performs real-time decoding of all resolutions in 16-pixel multiples, up to and including 720x480x30 or 720x576x25. Horizontal and vertical filters deliver high-quality video. Chrominance filtering and up-sampling to provide CCIR601 4:2:2 video output. Pan and scan are supported in 1/16 pel accuracy for 16:9 source material. Video rates range from 1.5 Mbps to 15 Mbps (higher in bursts). The MPEG-2 video decoder supports the European DVB standard and accepts Packetized Elementary or Elementary MPEG-2 streams. It uses Packetized Elementary Stream (PES) video decoding to extract the Presentation Time Stamp (PTS), and handles user data and other PES layer bit fields through memory access from the PPC405B3. Input can be from transport or directly from system memory. Outputs are provided for video-only and for video-with-OSD. The decoder can insert data in the vertical blanking interval (VBI) with VBI Output Support. It supports decoding of still or fixed images and display of scaled video images. It also features: * * * * * * * * * * * * * Letterbox format display Selectable anti-flicker filtering Output interface flexibility (programmable controls) Composite blanking and Field ID signals V-sync and H-sync signals CCIR656 master and slave modes Programmable signal polarity Sophisticated error concealment 3:2 pull-down support. Closed caption, teletext, or mixed (VPS) (1/4x, 1/2x, 2x) and three graphic planes Automated video channel change and time-base change features Blending of external graphics. A multi-plane on-screen display (OSD) uses bitmap data in memory to be merged with or displayed in place of the motion video data. Three OSD planes (the cursor, graphics and image planes) are provided for increased display flexibility. The OSD includes: * * * * * * * * * * * * * Programmable background color Multi-region link list graphic and image plane OSD with a color table for each region Programmable bitmap resolution on a region-by-region basis 64 x 64 pixel, 16-color cursor plane with blending controls Overlay and video blending of graphic plane Enhanced color mode for 24-bit color (YUV) in Direct Color and CLUT modes with 8-bit alpha blending Video shading in graphic plane OSD area OSD control output for external multiplexer (picture-in-picture support) Tiling capability in image and graphic planes Scrolling of image and graphic planes Horizontal scaling of image plane bitmaps Animation support 16 MB OSD addressing range to support more and larger bitmaps. MPEG-2 Transport and DVB Descrambler The MPEG-2 transport demultiplexer provides ISO / IEC 13818-1 MPEG-2 transport system layer demultiplexing. Its integrated digital video broadcasting (DVB) descrambler complies with DVB system layer requirements and may be turned off for non-DVB applications. Peak input rates are 100-Mbps (parallel) or 60-Mbps STB03_sds_041800.fm.01 April 18, 2000 Architecture and Subsystem Information Page 9 of 55 IBM39STB032XX IBM39STB034xx STB032xx and STB034xx Digital Set-Top Box Integrated Controllers Preliminary (serial), or 88-Mbps (parallel) or 60-Mbps (serial) with the optional descrambler. Packet Identifier (PID) filtering is based on 32 programmable entries with detection and notification of errors and lost packets. Hardwarebased clock recovery on program clock references (PCRs) reduces processor load by: - Calculating clock difference between PCR and System Time Clock (STC) - Modulating output to drive an external VCXO - Using an optional internal clock-recovery algorithm based on clock difference Transport and descrambler features include: * Internal DVB (1.0 or 1.1) descrambler, including filtering and storage of eight control word pairs * Auxiliary output port for real-time data transfers: - 8-bit mode at 1X, 1/2X, 1/3X, 1/4X and 1/8X of the system clock speed * Table section filtering: - 64 separate 4-byte filter blocks with bit-level masking with full match/not match capability - Multiple filters can be linked to extend filtering depth in 4-byte increments - Multiple filters per PID - Filters program-specific information (PSI), service information (SI), private tables - Handles multiple sections per packet and sections that span packets - Optional CRC checking of section data * Selective routing of some or all packet data to system memory: - Based on 32 separate queues (one per PID) - Routing entire packets, payloads, adaptation fields, table sections (after filtering) and private data * Direct transfer of audio / video (PES) data to decoders * Simplified channel changes, time-base changes and error flagging / concealment through direct communication with decoders * Interface for a Transport Assist Processor to provide additional processing: - Extended filtering / parsing of tables, private data, adaptation fields, and PES headers - Ability to selectively route alternative data fields to system memory MPEG-2/Dolby Digital Audio Decoder The Audio Decoder receives and decodes either ES (Elementary Stream) or PES (Packetized Elementary Stream) audio data. The audio compute engine is a generic DSP processor that decodes MPEG, Dolby Digital1, or 16-, 18- or 20-bit unformatted Pulse Code Modulation (PCM) audio data via individual software programs. The host processor downloads each program load to the Audio Decoder following initialization. The Audio Decoder generates up to two channels of decoded PCM for MPEG and PCM audio playback output. It provides 2-channel MPEG audio output and 6-channel Dolby Digital down-mixed to either two channels or six channels of Dolby Digital output. Unpacketized PCM (UPCM) plays back at sampling frequencies of 16 kHz, 22.05 kHz, 24 kHz, 32 kHz, 44.1 kHz, and 48 kHz, along with quantization sample width selections of 16-, 18or 20-bit input and 16 or 20-bit output. The Audio Decoder: * Decodes Dolby Digital, described in the ATSC Specification "Digital Audio Compression" (A/52). * Decodes MPEG-1 and MPEG-2 audio (Layers I and II) and 2-channel output, including single channel, stereo, joint stereo, and dual channel modes. 1. This feature available only on STB03x1x, Dolby Digital license required Architecture and Subsystem Information Page 10 of 55 STB03_sds_041800.fm.01 April 18, 2000 Preliminary IBM39STB032XX IBM39STB034xx STB032xx and STB034xx Digital Set-Top Box Integrated Controllers * Performs MPEG-1 and MPEG-2 PES audio parsing, and also accepts audio elementary streams. Parses and stores ancillary data into external memory for later use by the host processor. * Supports 16-kHz, 22.05-kHz, 24-kHz, 32-kHz, 44.1-kHz, and 48-kHz audio sampling frequencies. * Supports audio/video synchronization through PTS/STC comparison with each audio frame. * Supports Karaoke Mode for Dolby Digital and PCM playback. * Supports an encoded audio bit rate up to 640 Kbps. This bit rate only pertains to encoded bitstream data. * Includes Audio Clip Mode for PES, ES, and PCM formats with byte address granularity and 2MB maximum per clip buffer. * Allows PCM Mixing with primary audio stream input including sample rate conversion. PCM audio data supplied via secondary clip mode feature. * Supports expandable rate buffer size selectable from 4K to 64K (in 4K increments). * Uses a re-locatable rate buffer region, with a programmable base register (128-byte location granularity). * Has a re-locatable PTS Value and Ancillary data region, using a programmable base register with 128byte location granularity. * Uses a locatable Audio Temporary Data and Decoded Audio Data Bank region (programmable base register with 128-byte location granularity with additional offset register). * Includes 256x and 512x DAC sampling clock frequency configurations. * Has a programmable stream ID register with corresponding 8-bit enable field. * Provides three PCM output formats in 16- or 20-bit precision: - I2S - Left-justified - Right-justified * Performs audio bitstream error concealment, either by frame repeats or muting, due to loss of synchronization or detection of CRC errors. * Performs MPEG error checking using frame size calculation for each frame. * Provides de-emphasis pins that interface to external de-emphasis circuitry. * Provides Dolby Surround Mode (dsurmod) pins that interface to external surround mode circuitry. * Provides a programmable interface that supports the following: - Play, stop, and mute - Rate buffer purge to support channel and mode changes - Provides a compressed buffer full indicator - Synchronization enable/disable for PTS-STC comparison * Includes SPDIF meeting IEC61937 and IEC60958 specs. * Supports enhanced IEC61937 S/P DIF Channel Status bit by including 16 SPDIF Channel Status bits, with host control over most of the bits. * Inserts host-controlled validity bit into SPDIF sub-frame via DCR register. STB03_sds_041800.fm.01 April 18, 2000 Architecture and Subsystem Information Page 11 of 55 IBM39STB032XX IBM39STB034xx STB032xx and STB034xx Digital Set-Top Box Integrated Controllers Preliminary * Performs audio attenuation in 64 steps, with smooth transitions between steps. * Provides tone generation with up to 128 generated tones at 31 different durations with seven levels of attenuation via processor command. * Supports automated channel change. * Supports automated time base change. NTSC/PAL Digital Encoder Unit with Macrovision Copy Protection1 The multi-standard Digital Encoder converts digital audio/video data into analog National Television System Committee (NTSC) or Phase Alternate Line (PAL) data output formats (see Macrovision Licensing on page 3). It provides up to six concurrent analog video outputs, including S-Video, composite video, YPbPr, and RGB. The encoder is compatible with SCART connectors, with support for Macrovision Copy Protection Revision 7. Analog outputs are driven by 10-bit D/A converters, operating at 27 MHz. The outputs drive standard video levels into 75- loads. It supports closed caption, teletext insertion, and Line 23 WSS (Wide-screen Signaling) per ITU-R BT.1119. There is a switchable pedestal with gain compensation. Playback of synchronized video data can be locked to the incoming composite video stream. Additional Interfaces External Graphics and Video (EGV) Port External Graphics and Video (EGV) ports provide flexibility for interfacing external graphics and video components. When the EGV is used as an output, its signals may be routed to an external graphics device or DENC. When used as an input, either the internal OSD graphics can be replaced with data from an external graphics device, or external digital video data (from an analog signal converted to digital via DSMD, for example) could replace the internally decoded MPEG video. In the latter case, the external digital video can be merged/blended with the internal OSD graphics. 1. This feature is available only on STB03xx1, Macrovision license required. Architecture and Subsystem Information Page 12 of 55 STB03_sds_041800.fm.01 April 18, 2000 Preliminary IBM39STB032XX IBM39STB034xx STB032xx and STB034xx Digital Set-Top Box Integrated Controllers Peripheral Subsystem Peripheral Subsystem GPT / PWM IEEE 1284 Other Subsystems Architecture and Subsystem Information SmartCard (2) IIC (2) 16550 Serial Com Infrared Serial Com GPIO Serial Control Port Modem Interface OPB OPB Bridge IBM STB03xxx General Purpose Timer The General Purpose Timer (GPT) is an on-chip peripheral bus (OPB) function that provides a separate time base counter and additional system timers beyond those defined in the PPC405B3. Three Inter-Character (IC) time-out timers are also implemented in this functional unit in the GPT. These timers receive the count signal inputs from other units they are timing. Each timer is a 10-bit down counter loaded with a programmable value (TOUT) upon the active edge of the count signal input. Once loaded, the IC timer counts down TOUT number of TCLK cycles until it reaches zero (that is, when the IC timer has expired). When a timer expires, it sets its corresponding bit in the IC interrupt status register. There is a separate time base inside the GPT, distinct from the time base within the PPC405B3. Two event timers capture unique input events and there are two compare timers with unique outputs. Separately configurable and programmable synchronization controls edge detection and output levels. There are two reset inputs, one for the entire GPT unit, and one for the time base. Pulse Width Modulation The pulse width modulation (PWM) function produces two square wave outputs with a variable duty cycle under program control. The duty cycle varies from 100 percent to zero percent in steps of 1/256. There is a control register with two bits for each PWM. This register controls the active status of the PWM, and determines what its inactive output level should be. When the PWM control register is set to disable a PWM, the 8bit period counter will be inactive to minimize power. The pulse width modulation portion of the GPT contains two identical blocks, each containing an 8-bit programmable and reloadable down counter and control logic. A time-base generator that is a free-running counter (TCLK based) generates the frequency of the pulse-width modulated output. STB03_sds_041800.fm.01 April 18, 2000 PLB0 Page 13 of 55 IBM39STB032XX IBM39STB034xx STB032xx and STB034xx Digital Set-Top Box Integrated Controllers Preliminary IEEE 1284 Parallel Port The IEEE 1284 Parallel Port is implemented as either the host side or peripheral side of the parallel port data bus. The parallel port bidirectional interface supports IEEE Std. 1284 extended capability port (ECP)1, byte2, nibble3, and compatibility4 modes of operation. The parallel port also monitors IEEE Std. 1284 negotiation mode events, which allows the host to determine the capabilities of an attached peripheral and to set the interface into one of the four operational modes. The parallel port supports byte-wide FIFO but does not support Enhanced Parallel Port (EPP) mode. Two Direct Memory Access (DMA) channels for transmit and receive allow independent data transfers from other peripherals. The IEEE 1284 Parallel Port is compatible with existing parallel port hosts, and an Inter-Character Time-out Facility provides support with the GPT/PWM. Inter-Integrated Circuit (IIC) Units Two unique IIC units are used to provide two independent IIC interfaces and provide a simple to use, highly programmable interface between the OPB and the industry standard IIC serial bus. They provide full management of all IIC bus protocols, compliant with Phillips Semiconductors I2C Specification, dated 1995, and support a fixed VDD IIC interface. These IICs can be programmed to operate as master, as slave, or as both master and slave on the IIC interface. In addition to sophisticated IIC bus protocol management, the IICs provide full data buffering between the OPB and the IIC bus. The IIC units offer 5 V tolerant I/O for both 100- and 400-kHz operation with 8-bit data transfers and 7-bit and 10-bit address decode/generation. There is one programmable interrupt request signal, two independent 4 x 1-byte data buffers, and 12 memory-mapped, fully programmable configuration registers. Smart Card Interface Units The Smart Card Interface Units handle communications between an Integrated Circuit Card and the host CPU. These 5 V tolerant I/O devices have a software-based control structure and are designed for use with asynchronous transmissions. They feature hardware activation/deactivation and reset with software overrides and byte-wide FIFO support. They are compatible with ISO/IEC 7816-3 and support T0 and T1 protocols. The Interface Units support 2-channel DMA with 8-bit memory-mapped registers and hardware error checking. An Inter-Character Time-out Facility provides timing support from the GPT/PWM. 16550 Serial Communication Controller The 16550 Serial Communication Controller is a universal asynchronous receiver/transmitter (UART) with FIFOs, and is compatible with the 16550 part numbers manufactured by National Semiconductor (NS) Corporation. It is also compatible with National Semiconductor 16450 (non-FIFO version). Serial interface characteristics are fully programmable with complete modem control functions and status reporting capability. The controller supports: * 5-, 6-, 7-, or 8-bit characters * Even, odd, or no parity bit generation and detection * 1-, 1.5-, or 2-stop-bit generation * Variable baud rate and a programmable baud rate generator 1. 2. 3. 4. ECP refers to the extended capability port. An asynchronous, byte-wide, bidirectional channel. Byte refers to an asynchronous, reverse (peripheral-to-host) channel, under the control of the host. Nibble refers to an asynchronous, reverse (peripheral-to-host) channel, under the control of the host. Compatibility refers to an asynchronous, byte-wide forward (host-to-peripheral) channel. Architecture and Subsystem Information Page 14 of 55 STB03_sds_041800.fm.01 April 18, 2000 Preliminary IBM39STB032XX IBM39STB034xx STB032xx and STB034xx Digital Set-Top Box Integrated Controllers There is also support for two DMA channels with a 16-byte FIFO for transmit/receive path. Internal loopback is provided for diagnostics and an Inter-Character Timeout Facility provides timing support from the GPT/PWM. Infrared Serial Communications Controller In addition to standard UART functions, the Serial/Infrared Communications Controller can use an alternate mode (IrDA mode) to transfer and receive infrared characters. IrDA transmissions are specified by the Infrared Data Association (IrDA) Specification 1.1. IrDA mode supports RS-232 and infrared communications up to 1.152 Mbps with automatic insertion/removal of standard ASYNC communication bits. The controller includes: * A programmable baud rate generator * Individual enable for receiver and transmitter interrupts * Internal loopback and auto-echo modes * Full-duplex operation * Programmable serial interface * Status reporting capability * Individual receiver and transmitter DMA support * Auto-handshaking mode for receiver and transmitter * Transmitter pattern generation capability * Serial clock frequency up to 1/2 system clock frequency * Inter-Character Timeout Facility support from the GPT/PWM Modem Interface The Modem Interface provides a glueless communication from the device to and from many standard and economical telephony CODECs (Note: CODECs are the Audio ADC/DAC devices). The PPC405B3 CPU and applicable software can be used to implement an inexpensive interface for a modem. The external interface supports industry standard 4-wire parameters, consisting of transmit data, receive data, clock, and frame sync. Two channels of DMA allow off-loading data from the CPU. The Modem Interface supports digital audio MIC input, status reporting, and interrupt generation. Serial Control Port The Serial Control Port (SCP) is a full-duplex, synchronous, character-oriented (byte) port that allows the exchange of data with other SCP bus-compatible serial devices. The SCP is a slave device to the OPB bus, and supports a three-wire interface to the serial port (receive, transmit, and clock). It provides a glueless serial interface to many microcontrollers, with clock inversion and reverse data. The port includes a programmable clock rate divider (Sysclk/4 to Sysclk/1024), and bit rate is supported up to 1/4 the frequency of the system clock. General Purpose I/O Controller The General Purpose I/O (GPIO) controller enables the multiplexing of module I/Os, with functions that include programmable open-drain output conversion, registered input and output functions, and simplified GPIO definition. STB03_sds_041800.fm.01 April 18, 2000 Architecture and Subsystem Information Page 15 of 55 IBM39STB032XX IBM39STB034xx STB032xx and STB034xx Digital Set-Top Box Integrated Controllers Preliminary Pin and I/O Information Pinout Diagram 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 A B C D E FG VDD33 H J K LM VDD25 N P R T U VW Y AA AB AC LEGEND: Ground I/O Pin Pin and I/O Information Page 16 of 55 STB03_sds_041800.fm.01 April 18, 2000 Preliminary IBM39STB032XX IBM39STB034xx STB032xx and STB034xx Digital Set-Top Box Integrated Controllers Signal Pins Sorted by Signal Name Signal AUD_VDDA0 AUD_VDDA1 BI_ADDRESS8 (MSB) BI_ADDRESS9 BI_ADDRESS10 BI_ADDRESS11 BI_ADDRESS12 BI_ADDRESS13 BI_ADDRESS14 BI_ADDRESS15 BI_ADDRESS16 BI_ADDRESS17 BI_ADDRESS18 BI_ADDRESS19 BI_ADDRESS20 BI_ADDRESS21 BI_ADDRESS22 BI_ADDRESS23 BI_ADDRESS24 BI_ADDRESS25 BI_ADDRESS26 BI_ADDRESS27 BI_ADDRESS28 BI_ADDRESS29 BI_ADDRESS30 BI_ADDRESS31 (LSB)/BI_WBE1 BI_CS0 BI_CS1 BI_CS2 BI_CS3 BI_DATA0 (MSB) BI_DATA1 Grid (Pin) Position N22 K20 AA2 AC3 AC4 AB5 AC5 AA5 AB9 AA9 AC8 AB8 AC7 AB7 AC6 AB6 AB4 Y6 AA6 Y7 AA7 Y8 AA8 Y10 AC9 AC10 Y13 AB12 AA12 AC12 AA13 AA14 Group PLL Analog PWR + GND BI_DATA2 PLL Analog PWR + GND BI_DATA3 Bus Interface Bus Interface Bus Interface Bus Interface Bus Interface Bus Interface Bus Interface Bus Interface Bus Interface Bus Interface Bus Interface Bus Interface Bus Interface Bus Interface Bus Interface Bus Interface Bus Interface Bus Interface Bus Interface Bus Interface Bus Interface Bus Interface Bus Interface Bus Interface Bus Interface Bus Interface Bus Interface Bus Interface Bus Interface Bus Interface BI_DATA4 BI_DATA5 BI_DATA6 BI_DATA7 BI_DATA8 BI_DATA9 BI_DATA10 BI_DATA11 BI_DATA12 BI_DATA13 BI_DATA14 BI_DATA15 (LSB) BI_OE BI_READY BI_RW BI_WBE0 CI_CLOCK CI_DATA0 (MSB) CI_DATA1 CI_DATA2 CI_DATA3 CI_DATA4 CI_DATA5 CI_DATA6 CI_DATA7 (LSB) CI_DATA_ENABLE CLK_VDDA DAC1_AGND0 DAC1_AGND1 DAC1_AGND2 Signal Grid (Pin) Position AB15 AB16 AB17 AA16 AA15 AC14 Y14 AC15 AC16 AC17 Y17 Y16 AB14 AB13 AC13 AA10 AB10 Y11 U20 Y23 Y22 W23 W21 W22 V20 V23 V21 V22 C9 L1 J1 G3 Group Bus Interface Bus Interface Bus Interface Bus Interface Bus Interface Bus Interface Bus Interface Bus Interface Bus Interface Bus Interface Bus Interface Bus Interface Bus Interface Bus Interface Bus Interface Bus Interface Bus Interface Bus Interface Channel Interface Channel Interface Channel Interface Channel Interface Channel Interface Channel Interface Channel Interface Channel Interface Channel Interface Channel Interface PLL Analog PWR + GND DAC Analog PWR + GND DAC Analog PWR + GND DAC Analog PWR + GND STB03_sds_041800.fm.01 April 18, 2000 Pin and I/O Information Page 17 of 55 IBM39STB032XX IBM39STB034xx STB032xx and STB034xx Digital Set-Top Box Integrated Controllers Preliminary Signal Pins Sorted by Signal Name (Continued) Signal DAC1_AVDD0 DAC1_AVDD1 DAC1_AVDD2 DAC1_AVDD3 DAC1_BOUT DAC1_BREF_OUT DAC1_GOUT DAC1_GREF_OUT DAC1_ROUT DAC1_RREF_OUT DAC1_VREF_IN DAC2_AGND0 DAC2_AGND1 DAC2_AGND2 DAC2_AVDD0 DAC2_AVDD1 DAC2_AVDD2 DAC2_AVDD3 DAC2_BOUT DAC2_BREF_OUT DAC2_GOUT DAC2_GREF_OUT DAC2_ROUT DAC2_RREF_OUT DAC2_VREF_IN DA_BIT_CLOCK DA_IEC_958 DA_LR_CHANNEL_CLOCK DA_OVERSAMPLING_CLO CK Grid (Pin) Position L3 K2 J3 G2 H4 F1 K3 L4 L2 H3 H2 M2 P3 U1 M1 N4 P4 T2 T3 U2 N3 N1 M3 T1 R3 V1 W1 V3 V2 Group DAC Analog PWR + GND DAC Analog PWR + GND DAC Analog PWR + GND DAC Analog PWR + GND Video and Graphics Video and Graphics Video and Graphics Video and Graphics Video and Graphics Video and Graphics Video and Graphics DAC Analog PWR + GND DAC Analog PWR + GND DAC Analog PWR + GND DAC Analog PWR + GND DAC Analog PWR + GND DAC Analog PWR + GND DAC Analog PWR + GND Video and Graphics Video and Graphics Video and Graphics Video and Graphics Video and Graphics Video and Graphics Video and Graphics Audio Audio Audio Audio Signal DA_SERIAL_DATA0 DV1_DATA0 (MSB) DV1_DATA1 DV1_DATA2 DV1_DATA3 DV1_DATA4 DV1_DATA5 DV1_DATA6 DV1_DATA7 (LSB) DV1_HSYNC DV1_PIXEL_CLOCK DV1_VSYNC EDMAC3_ACK/IDE_ACK EDMAC3_REQ/IDE_REQ GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND Grid (Pin) Position V4 E3 E2 E1 D2 D1 C2 C1 B3 F2 F4 F3 Y2 AA1 B1 B2 B22 B23 C21 D4 D20 Y4 Y20 AA3 AA21 AB1 AB2 AB22 AB23 Audio Video and Graphics Video and Graphics Video and Graphics Video and Graphics Video and Graphics Video and Graphics Video and Graphics Video and Graphics Video and Graphics Video and Graphics Video and Graphics Direct Memory Access Direct Memory Access Ground Ground Ground Ground Ground Ground Ground Ground Ground Ground Ground Ground Ground Ground Ground Group Pin and I/O Information Page 18 of 55 STB03_sds_041800.fm.01 April 18, 2000 Preliminary IBM39STB032XX IBM39STB034xx STB032xx and STB034xx Digital Set-Top Box Integrated Controllers Signal Pins Sorted by Signal Name (Continued) Signal GND GND GND GND GND GND GND GND GND GND GND GND GND GPIO_0 GPIO_1 GPIO_2 GPIO_3 GPIO_4 GPIO_5 GPIO_6 GPIO_7 GPIO_8 GPIO_9 GPIO_10 GPIO_11 GPIO_12 GPIO_13 GPIO_14 GPIO_15 GPIO_16 GPIO_17 GPIO_18 GPIO_19 GPIO_20 GPIO_21 Grid (Pin) Position AC1 AC2 AC22 AC23 A1 A2 A22 A23 C3 D12 M20 Y12 M4 N23 N21 G4 AC11 A15 H20 AA18 AC18 AB20 B7 A7 D7 B8 A8 D8 B9 AB11 AA11 G1 H1 J2 T4 Ground Ground Ground Ground Ground Ground Ground Ground Ground Ground Ground Ground Ground General Purpose I/O General Purpose I/O General Purpose I/O General Purpose I/O General Purpose I/O General Purpose I/O General Purpose I/O General Purpose I/O General Purpose I/O General Purpose I/O General Purpose I/O General Purpose I/O General Purpose I/O General Purpose I/O General Purpose I/O General Purpose I/O General Purpose I/O General Purpose I/O General Purpose I/O General Purpose I/O General Purpose I/O General Purpose I/O Group GPIO_22 GPIO_23 GPIO_24 GPIO_25 GPIO_26 GPIO_27 GPIO_28 GPIO_29 GPIO_30 GPIO_31 G_SYSTEM_CLOCK G_SYSTEM_RST I2C0_SCL I2C0_SDA INT0 INT1 INT2 INT3 MUX0_0 MUX0_1 MUX0_2 MUX0_3 MUX0_4 MUX0_5 MUX0_6 MUX0_7 MUX0_8 MUX0_9 MUX0_10 MUX0_11 MUX0_12 MUX0_13 MUX0_14 MUX0_15 MUX0_16 Signal Grid (Pin) Position R2 R1 P2 P1 N2 K4 K1 C6 G23 G21 C8 C7 U4 U3 AA17 AB3 J23 K22 K23 K21 J21 L23 L22 L21 L20 M21 N20 P21 P22 P23 M22 M23 J22 H21 H23 Group General Purpose I/O General Purpose I/O General Purpose I/O General Purpose I/O General Purpose I/O General Purpose I/O General Purpose I/O General Purpose I/O General Purpose I/O General Purpose I/O Global Global Inter-Integrated Circuit (IIC) Inter-Integrated Circuit (IIC) Interrupt Interrupt Interrupt Interrupt Multiplexed I/O Multiplexed I/O Multiplexed I/O Multiplexed I/O Multiplexed I/O Multiplexed I/O Multiplexed I/O Multiplexed I/O Multiplexed I/O Multiplexed I/O Multiplexed I/O Multiplexed I/O Multiplexed I/O Multiplexed I/O Multiplexed I/O Multiplexed I/O Multiplexed I/O STB03_sds_041800.fm.01 April 18, 2000 Pin and I/O Information Page 19 of 55 IBM39STB032XX IBM39STB034xx STB032xx and STB034xx Digital Set-Top Box Integrated Controllers Preliminary Signal Pins Sorted by Signal Name (Continued) Signal MUX0_17 MUX0_18 MUX0_19 MUX0_20 MUX0_21 MUX0_22 MUX0_23 MUX0_24 MUX0_25 MUX0_26 MUX0_27 MUX0_28 MUX0_29 MUX0_30 MUX0_31 MUX0_32 MUX0_33 MUX0_34 MUX1_0 MUX1_1 MUX1_2 MUX2_0 MUX2_1 MUX2_2 MUX2_3 MUX3_0 MUX3_1 MUX3_2 MUX3_3 MUX3_4 MUX3_5 MUX3_6 MUX3_7 MUX3_8 MUX3_9 MUX3_10 Grid (Pin) Position G20 B20 A21 C23 D23 E21 F21 F23 G22 F20 F22 E23 E22 D22 C22 B21 A20 H22 Y1 W2 W3 A3 B4 A4 B5 U23 U21 U22 T20 T23 T21 T22 R23 R21 R22 P20 Group Multiplexed I/O Multiplexed I/O Multiplexed I/O Multiplexed I/O Multiplexed I/O Multiplexed I/O Multiplexed I/O Multiplexed I/O Multiplexed I/O Multiplexed I/O Multiplexed I/O Multiplexed I/O Multiplexed I/O Multiplexed I/O Multiplexed I/O Multiplexed I/O Multiplexed I/O Multiplexed I/O Multiplexed I/O Multiplexed I/O Multiplexed I/O Multiplexed I/O Multiplexed I/O Multiplexed I/O Multiplexed I/O Multiplexed I/O Multiplexed I/O Multiplexed I/O Multiplexed I/O Multiplexed I/O Multiplexed I/O Multiplexed I/O Multiplexed I/O Multiplexed I/O Multiplexed I/O Multiplexed I/O Signal Reserved - Tie to 3.3 V SC0_CLK SC0_DETECT SC0_IO SC0_RESET SC0_VCC_COMMAND SC1_CLK SC1_DETECT SC1_IO SC1_RESET SC1_VCC_COMMAND SD1_ADDRESS0 (MSB) SD1_ADDRESS1 SD1_ADDRESS2 SD1_ADDRESS3 SD1_ADDRESS4 SD1_ADDRESS5 SD1_ADDRESS6 SD1_ADDRESS7 SD1_ADDRESS8 SD1_ADDRESS9 SD1_ADDRESS10 SD1_ADDRESS11 SD1_ADDRESS12 SD1_ADDRESS13 (LSB) SD1_CAS SD1_CLK SD1_CS0 SD1_DATA0 (MSB) SD1_DATA1 SD1_DATA2 SD1_DATA3 SD1_DATA4 SD1_DATA5 SD1_DATA6 SD1_DATA7 Grid (Pin) Position B6 AB21 Y18 AC21 AA23 AA22 AA19 AB18 AC19 AB19 AC20 C16 A17 B16 B17 D16 C17 D17 C18 D18 C19 B19 A19 B18 A18 B15 D14 A16 D10 B10 D11 B11 C12 A12 C13 D13 Global Smart Card Interface 0 Smart Card Interface 0 Smart Card Interface 0 Smart Card Interface 0 Smart Card Interface 0 Smart Card Interface 1 Smart Card Interface 1 Smart Card Interface 1 Smart Card Interface 1 Smart Card Interface 1 SDRAM1 Controller SDRAM1 Controller SDRAM1 Controller SDRAM1 Controller SDRAM1 Controller SDRAM1 Controller SDRAM1 Controller SDRAM1 Controller SDRAM1 Controller SDRAM1 Controller SDRAM1 Controller SDRAM1 Controller SDRAM1 Controller SDRAM1 Controller SDRAM1 Controller SDRAM1 Controller SDRAM1 Controller SDRAM1 Controller SDRAM1 Controller SDRAM1 Controller SDRAM1 Controller SDRAM1 Controller SDRAM1 Controller SDRAM1 Controller SDRAM1 Controller Group Pin and I/O Information Page 20 of 55 STB03_sds_041800.fm.01 April 18, 2000 Preliminary IBM39STB032XX IBM39STB034xx STB032xx and STB034xx Digital Set-Top Box Integrated Controllers Signal Pins Sorted by Signal Name (Continued) Signal SD1_DATA8 SD1_DATA9 SD1_DATA10 SD1_DATA11 SD1_DATA12 SD1_DATA13 SD1_DATA14 SD1_DATA15 (LSB) SD1_DQMH SD1_DQML SD1_RAS SD1_WE SERIAL1/INFRARED_CTS SERIAL1/INFRARED_RTS SERIAL1/INFRARED_RXD SERIAL1/INFRARED_TXD VDD25 VDD25 VDD25 VDD25 Grid (Pin) Position A13 B13 B12 A11 C11 A10 C10 A9 C14 B14 C15 A14 A6 D6 A5 C5 AA4 AA20 C4 C20 Group SDRAM1 Controller SDRAM1 Controller SDRAM1 Controller SDRAM1 Controller SDRAM1 Controller SDRAM1 Controller SDRAM1 Controller SDRAM1 Controller SDRAM1 Controller SDRAM1 Controller SDRAM1 Controller SDRAM1 Controller Serial1 / Infrared Serial1 / Infrared Serial1 / Infrared Serial1 / Infrared 2.5 V Power 2.5 V Power 2.5 V Power 2.5 V Power VDD25 VDD25 VDD25 VDD25 VDD25 VDD25 VDD25 VDD25 VDD25 VDD25 VDD25 VDD25 VDD33 VDD33 VDD33 VDD33 VDD33 VDD33 VDD33 VDD33 Signal Grid (Pin) Position D3 D5 D19 D21 E4 E20 W4 W20 Y3 Y5 Y19 Y21 D9 D15 J4 J20 R4 R20 Y9 Y15 Group 2.5 V Power 2.5 V Power 2.5 V Power 2.5 V Power 2.5 V Power 2.5 V Power 2.5 V Power 2.5 V Power 2.5 V Power 2.5 V Power 2.5 V Power 2.5 V Power 3.3 V Power 3.3 V Power 3.3 V Power 3.3 V Power 3.3 V Power 3.3 V Power 3.3 V Power 3.3 V Power STB03_sds_041800.fm.01 April 18, 2000 Pin and I/O Information Page 21 of 55 IBM39STB032XX IBM39STB034xx STB032xx and STB034xx Digital Set-Top Box Integrated Controllers . Preliminary Signal Pins Sorted by Pin Number Grid (Pin) Position A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 AA1 AA2 AA3 AA4 AA5 AA6 AA7 AA8 AA9 AA10 AA11 AA12 GND GND MUX2_0 MUX2_2 Signal Ground Ground Multiplexed I/O Multiplexed I/O Group Grid (Pin) Position AA13 AA14 AA15 AA16 AA17 AA18 AA19 AA20 AA21 AA22 AA23 AB1 AB2 AB3 AB4 AB5 AB6 AB7 AB8 AB9 AB10 AB11 AB12 AB13 AB14 AB15 AB16 AB17 AB18 AB19 AB20 AB21 AB22 AB23 AC1 Signal BI_DATA0 (MSB) BI_DATA1 BI_DATA6 BI_DATA5 INT0 GPIO_6 SC1_CLK VDD25 GND SC0_VCC_COMMAND SC0_RESET GND GND INT1 BI_ADDRESS22 BI_ADDRESS11 BI_ADDRESS21 BI_ADDRESS19 BI_ADDRESS17 BI_ADDRESS14 BI_RW GPIO_16 BI_CS1 BI_DATA15 (LSB) BI_DATA14 BI_DATA2 BI_DATA3 BI_DATA4 SC1_DETECT SC1_RESET GPIO_8 SC0_CLK GND GND GND Group Bus Interface Bus Interface Bus Interface Bus Interface Interrupt General Purpose I/O Smart Card Interface 1 2.5 V Power Ground Smart Card Interface 0 Smart Card Interface 0 Ground Ground Interrupt Bus Interface Bus Interface Bus Interface Bus Interface Bus Interface Bus Interface Bus Interface General Purpose I/O Bus Interface Bus Interface Bus Interface Bus Interface Bus Interface Bus Interface Smart Card Interface 1 Smart Card Interface 1 General Purpose I/O Smart Card Interface 0 Ground Ground Ground SERIAL1/INFRARED_RXD Serial1 / Infrared SERIAL1/INFRARED_CTS GPIO_10 GPIO_13 SD1_DATA15 (LSB) SD1_DATA13 SD1_DATA11 SD1_DATA5 SD1_DATA8 SD1_WE GPIO_4 SD1_CS0 SD1_ADDRESS1 SD1_ADDRESS13 (LSB) SD1_ADDRESS11 MUX0_33 MUX0_19 GND GND EDMAC3_REQ/IDE_REQ BI_ADDRESS8 (MSB) GND VDD25 BI_ADDRESS13 BI_ADDRESS24 BI_ADDRESS26 BI_ADDRESS28 BI_ADDRESS15 BI_READY GPIO_17 BI_CS2 Serial1 / Infrared General Purpose I/O General Purpose I/O SDRAM1 Controller SDRAM1 Controller SDRAM1 Controller SDRAM1 Controller SDRAM1 Controller SDRAM1 Controller General Purpose I/O SDRAM1 Controller SDRAM1 Controller SDRAM1 Controller SDRAM1 Controller Multiplexed I/O Multiplexed I/O Ground Ground Direct Memory Access Bus Interface Ground 2.5 V Power Bus Interface Bus Interface Bus Interface Bus Interface Bus Interface Bus Interface General Purpose I/O Bus Interface Pin and I/O Information Page 22 of 55 STB03_sds_041800.fm.01 April 18, 2000 Preliminary IBM39STB032XX IBM39STB034xx STB032xx and STB034xx Digital Set-Top Box Integrated Controllers Signal Pins Sorted by Pin Number (Continued) Grid (Pin) Position AC2 AC3 AC4 AC5 AC6 AC7 AC8 AC9 AC10 AC11 AC12 AC13 AC14 AC15 AC16 AC17 AC18 AC19 AC20 AC21 AC22 AC23 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 GND BI_ADDRESS9 BI_ADDRESS10 BI_ADDRESS12 BI_ADDRESS20 BI_ADDRESS18 BI_ADDRESS16 BI_ADDRESS30 BI_ADDRESS31 (LSB)/BI_WEB1 GPIO_3 BI_CS3 BI_OE BI_DATA7 BI_DATA9 BI_DATA10 BI_DATA11 GPIO_7 SC1_IO SC1_VCC_COMMAND SC0_IO GND GND GND GND DV1_DATA7 (LSB) MUX2_1 MUX2_3 Reserved - Tie to 3.3 V GPIO_9 GPIO_12 GPIO_15 SD1_DATA1 SD1_DATA3 SD1_DATA10 SD1_DATA9 SD1_DQML Signal Ground Bus Interface Bus Interface Bus Interface Bus Interface Bus Interface Bus Interface Bus Interface Bus Interface General Purpose I/O Bus Interface Bus Interface Bus Interface Bus Interface Bus Interface Bus Interface General Purpose I/O Smart Card Interface 1 Smart Card Interface 1 Smart Card Interface 0 Ground Ground Ground Ground Video and Graphics Multiplexed I/O Multiplexed I/O Global General Purpose I/O General Purpose I/O General Purpose I/O SDRAM1 Controller SDRAM1 Controller SDRAM1 Controller SDRAM1 Controller SDRAM1 Controller Group Grid (Pin) Position B15 B16 B17 B18 B19 B20 B21 B22 B23 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 C16 C17 C18 C19 C20 C21 C22 C23 D1 D2 D3 D4 SD1_CAS SD1_ADDRESS2 SD1_ADDRESS3 SD1_ADDRESS12 SD1_ADDRESS10 MUX0_18 MUX0_32 GND GND DV1_DATA6 DV1_DATA5 GND VDD25 SERIAL1/INFRARED_TXD GPIO_29 G_SYSTEM_RST G_SYSTEM_CLOCK CLK_VDDA SD1_DATA14 SD1_DATA12 SD1_DATA4 SD1_DATA6 SD1_DQMH SD1_RAS SD1_ADDRESS0 (MSB) SD1_ADDRESS5 SD1_ADDRESS7 SD1_ADDRESS9 VDD25 GND MUX0_31 MUX0_20 DV1_DATA4 DV1_DATA3 VDD25 GND Signal Group SDRAM1 Controller SDRAM1 Controller SDRAM1 Controller SDRAM1 Controller SDRAM1 Controller Multiplexed I/O Multiplexed I/O Ground Ground Video and Graphics Video and Graphics Ground 2.5 V Power Serial1 / Infrared General Purpose I/O Global Global PLL Analog PWR + GND SDRAM1 Controller SDRAM1 Controller SDRAM1 Controller SDRAM1 Controller SDRAM1 Controller SDRAM1 Controller SDRAM1 Controller SDRAM1 Controller SDRAM1 Controller SDRAM1 Controller 2.5 V Power Ground Multiplexed I/O Multiplexed I/O Video and Graphics Video and Graphics 2.5 V Power Ground STB03_sds_041800.fm.01 April 18, 2000 Pin and I/O Information Page 23 of 55 IBM39STB032XX IBM39STB034xx STB032xx and STB034xx Digital Set-Top Box Integrated Controllers Preliminary Signal Pins Sorted by Pin Number (Continued) Grid (Pin) Position D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 D20 D21 D22 D23 E1 E2 E3 E4 E20 E21 E22 E23 F1 F2 F3 F4 F20 F21 F22 F23 G1 VDD25 SERIAL1/INFRARED_RTS GPIO_11 GPIO_14 VDD33 SD1_DATA0 (MSB) SD1_DATA2 GND SD1_DATA7 SD1_CLK VDD33 SD1_ADDRESS4 SD1_ADDRESS6 SD1_ADDRESS8 VDD25 GND VDD25 MUX0_30 MUX0_21 DV1_DATA2 DV1_DATA1 DV1_DATA0 (MSB) VDD25 VDD25 MUX0_22 MUX0_29 MUX0_28 DAC1_BREF_OUT DV1_HSYNC DV1_VSYNC DV1_PIXEL_CLOCK MUX0_26 MUX0_23 MUX0_27 MUX0_24 GPIO_18 Signal Group 2.5 V Power Serial1 / Infrared General Purpose I/O General Purpose I/O 3.3 V Power SDRAM1 Controller SDRAM1 Controller Ground SDRAM1 Controller SDRAM1 Controller 3.3 V Power SDRAM1 Controller SDRAM1 Controller SDRAM1 Controller 2.5 V Power Ground 2.5 V Power Multiplexed I/O Multiplexed I/O Video and Graphics Video and Graphics Video and Graphics 2.5 V Power 2.5 V Power Multiplexed I/O Multiplexed I/O Multiplexed I/O Video and Graphics Video and Graphics Video and Graphics Video and Graphics Multiplexed I/O Multiplexed I/O Multiplexed I/O Multiplexed I/O General Purpose I/O Grid (Pin) Position G2 G3 G4 G20 G21 G22 G23 H1 H2 H3 H4 H20 H21 H22 H23 J1 J2 J3 J4 J20 J21 J22 J23 K1 K2 K3 K4 K20 K21 K22 K23 L1 L2 L3 L4 L20 Signal DAC1_AVDD3 DAC1_AGND2 GPIO_2 MUX0_17 GPIO_31 MUX0_25 GPIO_30 GPIO_19 DAC1_VREF_IN DAC1_RREF_OUT DAC1_BOUT GPIO_5 MUX0_15 MUX0_34 MUX0_16 DAC1_AGND1 GPIO_20 DAC1_AVDD2 VDD33 VDD33 MUX0_2 MUX0_14 INT2 GPIO_28 DAC1_AVDD1 DAC1_GOUT GPIO_27 AUD_VDDA1 MUX0_1 INT3 MUX0_0 DAC1_AGND0 DAC1_ROUT DAC1_AVDD0 DAC1_GREF_OUT MUX0_6 Group DAC Analog PWR + GND DAC Analog PWR + GND General Purpose I/O Multiplexed I/O General Purpose I/O Multiplexed I/O General Purpose I/O General Purpose I/O Video and Graphics Video and Graphics Video and Graphics General Purpose I/O Multiplexed I/O Multiplexed I/O Multiplexed I/O DAC Analog PWR + GND General Purpose I/O DAC Analog PWR + GND 3.3 V Power 3.3 V Power Multiplexed I/O Multiplexed I/O Interrupt General Purpose I/O DAC Analog PWR + GND Video and Graphics General Purpose I/O PLL Analog PWR + GND Multiplexed I/O Interrupt Multiplexed I/O DAC Analog PWR + GND Video and Graphics DAC Analog PWR + GND Video and Graphics Multiplexed I/O Pin and I/O Information Page 24 of 55 STB03_sds_041800.fm.01 April 18, 2000 Preliminary IBM39STB032XX IBM39STB034xx STB032xx and STB034xx Digital Set-Top Box Integrated Controllers Signal Pins Sorted by Pin Number (Continued) Grid (Pin) Position L21 L22 L23 M1 M2 M3 M4 M20 M21 M22 M23 N1 N2 N3 N4 N20 N21 N22 N23 P1 P2 P3 P4 P20 P21 P22 P23 R1 R2 R3 R4 R20 R21 R22 R23 MUX0_5 MUX0_4 MUX0_3 DAC2_AVDD0 DAC2_AGND0 DAC2_ROUT GND GND MUX0_7 MUX0_12 MUX0_13 DAC2_GREF_OUT GPIO_26 DAC2_GOUT DAC2_AVDD1 MUX0_8 GPIO_1 AUD_VDDA0 GPIO_0 GPIO_25 GPIO_24 DAC2_AGND1 DAC2_AVDD2 MUX3_10 MUX0_9 MUX0_10 MUX0_11 GPIO_23 GPIO_22 DAC2_VREF_IN VDD33 VDD33 MUX3_8 MUX3_9 MUX3_7 Signal Group Multiplexed I/O Multiplexed I/O Multiplexed I/O DAC Analog PWR + GND DAC Analog PWR + GND Video and Graphics Ground Ground Multiplexed I/O Multiplexed I/O Multiplexed I/O Video and Graphics General Purpose I/O Video and Graphics DAC Analog PWR + GND Multiplexed I/O General Purpose I/O PLL Analog PWR + GND General Purpose I/O General Purpose I/O General Purpose I/O DAC Analog PWR + GND DAC Analog PWR + GND Multiplexed I/O Multiplexed I/O Multiplexed I/O Multiplexed I/O General Purpose I/O General Purpose I/O Video and Graphics 3.3 V Power 3.3 V Power Multiplexed I/O Multiplexed I/O Multiplexed I/O Grid (Pin) Position T1 T2 T3 T4 T20 T21 T22 T23 U1 U2 U3 U4 U20 U21 U22 U23 V1 V2 V3 V4 V20 V21 V22 V23 W1 W2 W3 W4 W20 W21 W22 W23 Y1 Y2 Y3 Signal DAC2_RREF_OUT DAC2_AVDD3 DAC2_BOUT GPIO_21 MUX3_3 MUX3_5 MUX3_6 MUX3_4 DAC2_AGND2 DAC2_BREF_OUT I2C0_SDA I2C0_SCL CI_CLOCK MUX3_1 MUX3_2 MUX3_0 DA_BIT_CLOCK Group Video and Graphics DAC Analog PWR + GND Video and Graphics General Purpose I/O Multiplexed I/O Multiplexed I/O Multiplexed I/O Multiplexed I/O DAC Analog PWR + GND Video and Graphics Inter-Integrated Circuit (IIC) Inter-Integrated Circuit (IIC) Channel Interface Multiplexed I/O Multiplexed I/O Multiplexed I/O Audio DA_OVERSAMPLING_CLO Audio CK DA_LR_CHANNEL_CLOCK Audio DA_SERIAL_DATA0 CI_DATA5 CI_DATA7 (LSB) CI_DATA_ENABLE CI_DATA6 DA_IEC_958 MUX1_1 MUX1_2 VDD25 VDD25 CI_DATA3 CI_DATA4 CI_DATA2 MUX1_0 EDMAC3_ACK/IDE_ACK VDD25 Audio Channel Interface Channel Interface Channel Interface Channel Interface Audio Multiplexed I/O Multiplexed I/O 2.5 V Power 2.5 V Power Channel Interface Channel Interface Channel Interface Multiplexed I/O Direct Memory Access 2.5 V Power STB03_sds_041800.fm.01 April 18, 2000 Pin and I/O Information Page 25 of 55 IBM39STB032XX IBM39STB034xx STB032xx and STB034xx Digital Set-Top Box Integrated Controllers Preliminary Signal Pins Sorted by Pin Number (Continued) Grid (Pin) Position Y4 Y5 Y6 Y7 Y8 Y9 Y10 Y11 Y12 Y13 GND VDD25 BI_ADDRESS23 BI_ADDRESS25 BI_ADDRESS27 VDD33 BI_ADDRESS29 BI_WBE0 GND BI_CS0 Signal Ground 2.5 V Power Bus Interface Bus Interface Bus Interface 3.3 V Power Bus Interface Bus Interface Ground Bus Interface Group Grid (Pin) Position Y14 Y15 Y16 Y17 Y18 Y19 Y20 Y21 Y22 Y23 BI_DATA8 VDD33 BI_DATA13 BI_DATA12 SC0_DETECT VDD25 GND VDD25 CI_DATA1 CI_DATA0 (MSB) Signal Group Bus Interface 3.3 V Power Bus Interface Bus Interface Smart Card Interface 0 2.5 V Power Ground 2.5 V Power Channel Interface Channel Interface Pin and I/O Information Page 26 of 55 STB03_sds_041800.fm.01 April 18, 2000 Preliminary IBM39STB032XX IBM39STB034xx STB032xx and STB034xx Digital Set-Top Box Integrated Controllers STB03xxx Multiplexed I/O Signal Table STB03xxx has four sets of multiplexed I/O signals: Mux0, Mux1, Mux2, and Mux3. At reset, the multiplexed I/O signals are tristated, unless noted. The muxtiplexed I/O can be selected by column in the following tables. For example, if Input/Output 1 is selected, Input/Output 2 and Input/Output 3 are not available. Blank entries indicate reserved multiplexing. Multiplexed I/O Signal Table Bit # 00 01 02 03 04 05 06 07 08 09 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 Input/Output 1 SD0_ADDRESS0 (MSB) SD0_ADDRESS1 SD0_ADDRESS2 SD0_ADDRESS3 SD0_ADDRESS4 SD0_ADDRESS5 SD0_ADDRESS6 SD0_ADDRESS7 SD0_ADDRESS8 SD0_ADDRESS9 SD0_ADDRESS10 SD0_ADDRESS11 SD0_ADDRESS12 SD0_ADDRESS13 SD0_CS0 SD0_RAS SD0_CAS SD0_WE SD0_DATA0 SD0_DATA1 SD0_DATA2 SD0_DATA3 SD0_DATA4 SD0_DATA5 SD0_DATA6 SD0_DATA7 SD0_DATA8 SD0_DATA9 SD0_DATA10 Type O O O O O O O O O O O O O O O O O O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O Input/Output 2 IEEE1284_PD0 (MSB) IEEE1284_PD1 IEEE1284_PD2 IEEE1284_PD3 IEEE1284_PD4 IEEE1284_PD5 IEEE1284_PD6 IEEE1284_PD7 IEEE1284_AUTOFEED IEEE1284_SELECT_IN IEEE1284_BUSY IEEE1284_SELECT IEEE1284_PE IEEE1284_ERROR IEEE1284_ACK IEEE1284_PDIR IEEE1284_INIT IEEE1284_STROBE BI_DATA16 BI_DATA17 BI_DATA18 BI_DATA19 BI_DATA20 BI_DATA21 BI_DATA22 BI_DATA23 BI_DATA24 BI_DATA25 BI_DATA26 Type I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O STB03_sds_041800.fm.01 April 18, 2000 Pin and I/O Information Page 27 of 55 IBM39STB032XX IBM39STB034xx STB032xx and STB034xx Digital Set-Top Box Integrated Controllers Preliminary Multiplexed I/O Signal Table (Continued) Bit # 29 30 31 32 33 34 SD0_DATA11 SD0_DATA12 SD0_DATA13 SD0_DATA14 SD0_DATA15 SD0_CLK Input/Output 1 Type I/O I/O I/O I/O I/O O BI_DATA27 BI_DATA28 BI_DATA29 BI_DATA30 BI_DATA31 (LSB) IEEE1284_HOST Input/Output 2 Type I/O I/O I/O I/O I/O O Multiplexed I/O Signal Table - Mux1 Bit # 00 01 02 EDMAC2_ACK EDMAC2_REQ EDMAC2_EOT Input/Output 1 O I I/O Type Input/Output 2 EBM_HOLDACK EBM_HOLDREQ EBM_BUSREQ Type I/O I/O I/O Multiplexed I/O Signal Table - Mux2 Bit # 00 01 02 03 Input/Output 1 SERIAL0/16550_TXD SERIAL0/16550_RXD SERIAL0/16550_CTS SERIAL0/16550_RTS O I I O Type SSP_TXD SSP_RXD SSP_CLK SSP_FS Input/Output 2 O I I I/O Type Multiplexed I/O Signal Table - Mux3 Bit # Input/Output 1 Type Input/Output 2 Type Input/Output 3 SERIAL1/INFRARE D_DSR (through GPIO bit 31 alt rcv 2) SERIAL1/INFRARE D_DTR RW_TMS (through GPIO bit 11 alt rcv 1 RW_TDI (through GPIO bit 12 alt rcv 1) RW_TCK (through GPIO bit 13 alt rcv 1) Type Input/Output 4 Type O I RT_TS1E 00 HSP_DATA0 O IEEE1284_PD0 (MSB) I/O 01 HSP_DATA1 O IEEE1284_PD1 I/O O RT_TS2E O O 02 HSP_DATA2 O IEEE1284_PD2 I/O I RT_TS1O O I RT_TS2O 03 HSP_DATA3 O IEEE1284_PD3 I/O O I RT_TS3 04 HSP_DATA4 O IEEE1284_PD4 I/O Pin and I/O Information Page 28 of 55 STB03_sds_041800.fm.01 April 18, 2000 Preliminary IBM39STB032XX IBM39STB034xx STB032xx and STB034xx Digital Set-Top Box Integrated Controllers Multiplexed I/O Signal Table - Mux3 (Continued) Bit # 05 Input/Output 1 HSP_DATA5 Type O Input/Output 2 IEEE1284_PD5 Type I/O Input/Output 3 RW_TDO RW_HALT (through GPIO bit 15 alt rcv 1) SERIAL0/16550_DS R (through GPIO bit 5 alt rcv 3) SERIAL0/16550_DT R SERIAL0/16550_DC D (through GPIO bit 6 alt rcv 3) SERIAL0/16550_RI (through GPIO bit 8 alt rcv 3) Type O Input/Output 4 RT_TS4 Type O O 06 HSP_DATA6 O IEEE1284_PD6 I/O I RT_TS5 O I RT_TS6 07 HSP_DATA7 O IEEE1284_PD7 I/O 08 HSP_CLOCK O IEEE1284_ STROBE I/O O RT_CLK O 09 HSP_DATA_ ENABLE O IEEE1284_ACK I/O I 10 HSP_PACKET_ START O IEEE1284_INIT I/O I STB03_sds_041800.fm.01 April 18, 2000 Pin and I/O Information Page 29 of 55 IBM39STB032XX IBM39STB034xx STB032xx and STB034xx Digital Set-Top Box Integrated Controllers Preliminary General Purpose I/O (GPIO) The following table describes the GPIO bits. For each GPIO bit only one signal can be selected at a time. Each table row lists the signal associated with each logical GPIO bit number. The first column lists the GPIO bit number. The second column lists the signal connected as input or output to the first alternate GPIO multiplexer. The signal name is listed first, followed by the signal description. The third column gives the direction of the signal listed in column 2. The same format is used for columns 4 through 7. Blank entries indicate reserved GPIO multiplexing. GPIO bit number refers to the device GPIO signal name, not the physical device pin number. After reset all GPIOs are programmed as inputs, with the exception of GPIO0 bit 29 (PWM output), which defaults to an open-drain output, and GPIO bit 14 (JTAG TDO output), which defaults to an output (if BI_DATA[4] is set to `0' during reset). General Purpose I/O Bits Bit # 00 01 02 03 04 05 06 07 08 09 10 11 12 13 14 15 16 17 18 Input/Output Mux 1 I2C1_SCL I2C1_SDA AV_CSYNC BI_CS4 SYS_CLK EDMAC0_REQ EDMAC0_ACK SCP_TXD SCP_RXD SCP_CLK PWM0 PWM1 RW_TMS RW_TDI RW_TCK RW_TDO RW_HALT DA_SERIAL_DATA1 DA_SERIAL_DATA2 DV_TRANSPARENCY_ GATE Type I/O I/O I O O I O O I O O O I I I O I O O I/O Input/Output Mux 2 DA_DEEMPHASIS0 DA_DEEMPHASIS1 GPT_FreqGenOut BI_CS5 SD1_CS1 SD0_CS1 CI_PACKET_START CI_DATA_ERROR TS_REQ GPT_COMP0 GPT_COMP1 SSP_TXD SSP_RXD SSP_CLK SSP_FS SERIAL0/16550_CLK - External SERIAL0/16550 Clock Input BI_CS4 BI_CS5 DV2_PIXEL_CLOCK I Type O O O O O O I I O O Input/Output Mux 3 DA_SURMOD0 DA_SURMOD1 DA_SURMOD0 INT4 DA_SURMOD1 INT5 SERIAL0/16550_DTR SERIAL0/16550_DSR SERIAL0/16550_DCD TS_BCLKEN SERIAL0/16550_RI GPT_CAPT0 BI_CS6 GPT_CAPT1 BI_CS7 BI_CS6 BI_CS7 INT6 INT7 SYS_CLK Type O O O I O I O I I I I I O I O O O I I O O O I I I/O I O O HSP_ERROR SERIAL1/INFRARED_CLK External SERIAL1/INFRARED Clock Input O I Pin and I/O Information Page 30 of 55 STB03_sds_041800.fm.01 April 18, 2000 Preliminary IBM39STB032XX IBM39STB034xx STB032xx and STB034xx Digital Set-Top Box Integrated Controllers General Purpose I/O Bits (Continued) Bit # 19 20 21 22 23 24 25 26 27 28 29 30 31 Input/Output Mux 1 TTX_REQ TTX_DATA DV2_DATA0 (MSB) DV2_DATA1 DV2_DATA2 DV2_DATA3 DV2_DATA4 DV2_DATA5 DV2_DATA6 DV2_DATA7 DENC_PWM_OUTPUT EDMAC1_REQ BI_WBE2 EDMAC1_ACK Type I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O O I O O Input/Output Mux 2 DV2_VSYNC DV2_HSYNC IEEE1284_AUTOFEED IEEE1284_SELECT_IN IEEE1284_BUSY IEEE1284_SELECT IEEE1284_PE IEEE1284_ERROR IEEE1284_PDIR IEEE1284_HOST XPT_PWM_OUTPUT SERIAL1/INFRARED_DTR SERIAL1/INFRARED_DSR BI_WBE3 Type I/O I/O I/O I/O I/O I/O I/O I/O O O O O I O SD0_DQMH SD0_DQML O O INT8 INT9 I I Input/Output Mux 3 Type STB03_sds_041800.fm.01 April 18, 2000 Pin and I/O Information Page 31 of 55 IBM39STB032XX IBM39STB034xx STB032xx and STB034xx Digital Set-Top Box Integrated Controllers Preliminary Electrical Information The following tables give the absolute ratings for various electrical characteristics. Drivers/Receivers Four types of I/O drivers and receivers are used on the STB03xxx device, as follows: . I/O Driver Types Driver/ Receiver Type Characteristics Used on I/O signals: G_SYSTEM_RESET, GPIO[2], GPIO[29], SC0_IO, SC0_CLK, SC0_DETECT, SC0_RESET, SC0_VCC_COMMAND, SC1_IO, SC1_CLK, SC1_DETECT, SC1_RESET, SC1_VCC_COMMAND, BI_READY I2C0_SDA, I2C0_SCL, GPIO[0], GPIO[1] BI_DATA[0:15], MUX0[18:33] all other digital I/O signals BP3365 5 V tolerant, no pull-up or pull-down (external pull-up is required) BP3335 BT3350PU BT3365PU 5 V tolerant, no pull-up or pull-down (external pull-up is required) 3.3 V I/O with pull-up 3.3 V I/O with pull-up DC Electrical Characteristics The table, "DC Electrical Characteristics," gives the absolute ratings for various electrical characteristics. The temperature is 70 C in all cases. DC Electrical Characteristics Driver / Receiver Symbol VIH VIL BP3335 VOH VOL VIH VIL BP3365 VOH VOL Parameter High Level Input Voltage Low Level Input Voltage High Level Output Voltage Low Level Output Voltage High Level Input Voltage Low Level Input Voltage High Level Output Voltage Low Level Output Voltagec VCC = Min, IOH = 9.0 mA VCC = Min, IOL= 6.0 mA VCC = Min, IOH = 17.0 mA VCC = Min, IOL= 11.0 mA 2.00 -0.602 2.40 0.4 Conditions Min 2.00 -0.602 2.40 0.4 5.501 0.80 Typ Max 5.501 0.80 Units V V V V V V V V 1. Maximum VIH applies to overshoot only. 2. Minimum VIL applies to undershoot only. 3. 5.0 volt tolerant Driver/Receiver, see graph, page 34. Electrical Information Page 32 of 55 STB03_sds_041800.fm.01 April 18, 2000 Preliminary IBM39STB032XX IBM39STB034xx STB032xx and STB034xx Digital Set-Top Box Integrated Controllers DC Electrical Characteristics (Continued) Driver / Receiver Symbol VIH VIL BT3350PU VOH VOL VIH VIL BT3365PU VOH VOL BT3350PU, BT3365PU BP3335, BP33653 II II ICC ICC330 CI ESD PD Parameter High Level Input Voltage Low Level Input Voltage High Level Output Voltage Low Level Output Voltage High Level Input Voltage Low Level Input Voltage High Level Output Voltage Low Level Output Voltage Maximum Input Current Maximum Input Current Supply Current, 2.5 V Supply Current, 3.3 V Input Capacitance Electro Static Discharge Power Dissipation VCC = Max VCC330 = Max VCC = Nom, VI = Nom -3000 2.5 TBD TBD 2.6 3000 VCC = Min, IOH = 9.0 mA VCC = Min, IOL= 6.0 mA VIN = 0 V VCC = Min, IOH = 12.0 mA VCC = Min, IOL= 8.0 mA 2.00 -0.602 2.40 0.4 -250 Conditions Min 2.00 -0.602 2.40 0.4 4.01 0.80 Typ Max 4.01 0.80 Units V V V V V V V V A A mA mA pF V W N/A N/A All All N/A 1. Maximum VIH applies to overshoot only. 2. Minimum VIL applies to undershoot only. 3. 5.0 volt tolerant Driver/Receiver, see graph, page 34. STB03_sds_041800.fm.01 April 18, 2000 Electrical Information Page 33 of 55 IBM39STB032XX IBM39STB034xx STB032xx and STB034xx Digital Set-Top Box Integrated Controllers Preliminary BP33 Receiver Maximum Input Leakage DC Current Input Specifications Function Without pull-up element or pull-down element With pull-up element Iil (A) 0 at Vin = LPDL -250 at Vin = LPDL Iih (A) 0 at Vin = MPUL 0 at Vin = MPUL BP33 Receiver Input Current/Voltage Curve Current (A) 0.00 - 50.00 -100.00 -150.00 -200.00 -250.00 -300.00 -350.00 -400.00 -450.00 -500.00 -550.00 0.00 Note: 0C, 3.6V, best case process. 1.00 2.00 3.00 4.00 5.00 Voltage (V) The absolute maximum ratings in the following table are stress ratings only. Operation at or beyond these maximum ratings may cause permanent damage to the device. Electrical Information Page 34 of 55 STB03_sds_041800.fm.01 April 18, 2000 Preliminary . IBM39STB032XX IBM39STB034xx STB032xx and STB034xx Digital Set-Top Box Integrated Controllers Absolute Maximum Ratings Parameter Supply voltage with respect to GND, 2.5 V supply Supply voltage with respect to GND, 3.3 V supply Case temperature under bias Storage temperature Maximum Rating 3.0 V 3.9 V TBD -65 C to 150 C Operating Conditions The STB03xxx Digital Set-Top Box Integrated Controller can interface to either 3.3 V or 5 V technologies. 5 V interfaces are supported only for drivers/receivers supporting 5 V tolerance (see Drivers/Receivers). The range for supply voltages is specified for five-percent margins relative to a nominal 2.5 V and 3.3 V power supply. Note: Device operation beyond the conditions specified in the table below is not recommended. Extended operation beyond the recommended conditions may affect device reliability. Recommended Operating Conditions Symbol Parameter Min Max Unit VCC VCC330 TA Supply Voltage, 2.5 V Supply Voltage, 3.3 V Operating Free Air Temperature 2.38 3.14 0 2.62 3.47 70 V V C Power Considerations Power dissipation is determined by operating frequency, temperature, and supply voltage, as well as external source/sink current requirements. Power Sequencing The 2.5 V power supply must maintain the following relationship whenever the 3.3 V power supply voltage is greater than 0.4 V: 2.5 V power supply voltage >= 0.4 V Supply excursions outside this range must be limited to less than 25 ms duration during each power-up or power-down event. General Recommendation System designs that derive the 2.5 V supply from a regulator running from the 3.3 V supply are recommended to ensure a fixed relationship between the two voltage supplies. Such usage substantially reduces the potential for the 3.3 V supply to be present without the 2.5 V supply. Recommended Connections Power and ground pins should all be connected to separate power and ground planes in the circuit board to which the STB03xxx is mounted. Unused input pins must be tied inactive, either high or low. STB03_sds_041800.fm.01 April 18, 2000 Electrical Information Page 35 of 55 IBM39STB032XX IBM39STB034xx STB032xx and STB034xx Digital Set-Top Box Integrated Controllers Preliminary Recommended Connections for Analog I/O Pins DAC1_AVDD0 DAC1_AVDD1 DAC1_AVDD2 DAC1_AVDD3 DAC2_AVDD0 DAC2_AVDD1 DAC2_AVDD2 DAC2_AVDD3 L3 K2 J3 G2 M1 N4 P4 T2 1 nF 1 nF .1 mF .1 mF .1 mF .1 mF .1 mF 22 mF 1 nH 2.5 V DAC1_GREF_OUT DAC2_GREF_OUT DAC1_RREF_OUT DAC2_RREF_OUT L4 N1 H3 T1 784 784 (For a 75 W DAC Output Load) DAC1_BREF_OUT DAC2_BREF_OUT F1 U2 1 nF 1 nF CLK_VDDA C9 .1 mF 1.2 mF 2.5V AUD_VDDA0 AUD_VDDA1 N22 K20 .1 mF 5K 1.2 mH 2.5 V Electrical Information Page 36 of 55 STB03_sds_041800.fm.01 April 18, 2000 Preliminary IBM39STB032XX IBM39STB034xx STB032xx and STB034xx Digital Set-Top Box Integrated Controllers I/O Timing Diagrams AC Specification Note 1. Clock timing and switching characters are specified in accordance with operating conditions in Recommended Operating Conditions on page 35. AC specifications assume a 30 pF output load. All input slow rates must be 5 ns or less, unless otherwise specified (rise and fall times measured between 0.8 V and 2.0 V). Also, all input clocks must have a 40-60% duty cycle, unless otherwise specified. Note 2. The internal SysClk is shown in the diagrams to indicate the relationship of the number of cycles between various signal edges on the timing diagram. Note 3. Where multiple interfaces share the same timing diagram, the signals names are listed using an `n' to indicate that the timings apply to both interfaces. For example, the SD0 and SD1 interface signal names in the SDRAM interface timing diagram are listed as `SDn'. G_SysClk Timing TCR TCF 2.0 V 1.5 V 0.8 V TCH TC TCL SysClk Timing Values Symbol FC TCS TCH TCL TCR TCF SysClk clock input frequency Clock edge stability1 Clock input high time Clock input low time Clock input rise time2 Clock input fall time2 15 15 0.6 0.6 Parameter Min Max Units MHz ns ns ns ns ns (Nominal 27) 0.15 Note 1. Cycle-to-cycle jitter allowed between any two edges. Note 2. Rise and fall times measured between 0.8 V and 2.0 V. STB03_sds_041800.fm.01 April 18, 2000 Electrical Information Page 37 of 55 IBM39STB032XX IBM39STB034xx STB032xx and STB034xx Digital Set-Top Box Integrated Controllers Preliminary G_System_Reset Timing Power-On Timing Input VDD G_SYSTEM_CLOCK VALID Input t1 G_SYSTEM_RESET t2 Configuration Pins (BI_DATA[0:7], MUX2[0]) Edge Timing t4 G_SYSTEM_RESET t5 2.0 V 0.8 V t3 Input VALID Input G_SYSTEM_RESET Timing Values Symbol T1 T2 T3 T4 T5 Clock to Reset inactive Input setup time Input hold time Input rise time Input fall time Parameter Min 152 0 80 37 37 Max Units s ns ns ns ns Note: External logic must drive G_SYSTEM_RESET low during power-on, using an open-drain driver. Electrical Information Page 38 of 55 STB03_sds_041800.fm.01 April 18, 2000 Preliminary IBM39STB032XX IBM39STB034xx STB032xx and STB034xx Digital Set-Top Box Integrated Controllers SRAM Interface Timing t1 Internal SYSCLK t2 BI_ADDRESS t4 BI_CS t6 BI_OE t8 BI_WBE t10 BI_R/W TWT +1 t12 BI_DATA (to STB03xxx) t14 BI_DATA (from STB03xxx) t13 VALID t15 Output Input t11 Output t9 Output t7 Output VALID t5 Output t3 Output Output SRAM Interface Timing Values Symbol T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 At SYSCLK = 54 MHz Address output valid time Address output hold time Chip Select output valid time Chip Select output hold time Output Enable output valid time Output Enable output hold time Write Byte Enable output valid time Write Byte Enable output hold time Read/Write output valid time Read/Write output hold time Data input setup time 3 7 3 12 3 12 3 12 3 12 Parameter Min Max 19.25 12 Units ns ns ns ns ns ns ns ns ns ns ns ns STB03_sds_041800.fm.01 April 18, 2000 Electrical Information Page 39 of 55 IBM39STB032XX IBM39STB034xx STB032xx and STB034xx Digital Set-Top Box Integrated Controllers Preliminary SRAM Interface Timing Values (Continued) Symbol T13 T14 T16 Data input hold time Data output valid time Data output hold time 3 Parameter Min 3 15 Max Units ns ns ns SDRAM Interface Timing Diagram t1 SDn_CLK Output SDn_DATA, Controls t2 SDn_DATA VALID Output t3 Input t4 t5 SDRAM Interface Timing Values Symbol T1 T2 T3 T4 T5 Parameter SD_clk clock period (at SYSCLK = 54 MHz) Output valid time Output hold time Input setup time Input hold time 1 1 2.5 Min 9.25 7.25 Max Units ns ns ns ns ns Notes: TRCD = (2, 3, or 4) x t1 - controlled by SDRAMC Bank Register bits [21:22] TRAS = (5 or 6) x t1 - controlled by SDRAMC System Register bit 4 TRP = (2, 3, or 4) x t1 - controlled by SDRAMC Bank Register bits [25:26] TRC = (7, 8, 9, or 10) x t1 - controlled by SDRAMC Bank Register bits [30:31] Electrical Information Page 40 of 55 STB03_sds_041800.fm.01 April 18, 2000 Preliminary IBM39STB032XX IBM39STB034xx STB032xx and STB034xx Digital Set-Top Box Integrated Controllers Video Input Interface Timing t1 DVn_PIXEL_CLOCK Input DVn_VSYNC VALID t2 t3 Input DVn_DATA DVn_HSYNC VALID t4 t3 Input Video Input Timing Values Symbol T1 T2 T3 T4 Pixel clock period Input setup time Input hold time Input setup time 16 4 11 Parameter Min Max 37 Units ns ns ns Video Output Interface Timing t1 DVn_PIXEL_CLOCK Output DVn_DATA DVn_HSYNC DVn_VSYNC t2 VALID t3 Output Video Output Timing Values Symbol T1 T2 T3 Pixel Clock period Output valid time Output hold time 4 Parameter Min Max 37 15 Units ns ns ns STB03_sds_041800.fm.01 April 18, 2000 Electrical Information Page 41 of 55 IBM39STB032XX IBM39STB034xx STB032xx and STB034xx Digital Set-Top Box Integrated Controllers Preliminary Transport Input Interface Timing t1 Input CI_CLOCK CI_DATA CI_PACKET_START CI_DATA_ENABLE t2 t3 VALID Input Transport Input Interface Timing Values Symbol T1 T2 T3 Parameter CI_CLOCK period Input setup time Input hold time Min 15 4 3 Max Units ns ns ns Transport Auxiliary Output Interface Timing t1 HSP_CLOCK Output HSP_DATA HSP_DATA_ENABLE HSP_PACKET_START t2 VALID Output t3 Transport Auxiliary Output Interface Timing Values Symbol T1 T2 T3 Parameter HSP_clock period (at SYSCLK = 54 MHz) Output valid time Output hold time 2 Min 19.25 10 Max Units ns ns ns Electrical Information Page 42 of 55 STB03_sds_041800.fm.01 April 18, 2000 Preliminary IBM39STB032XX IBM39STB034xx STB032xx and STB034xx Digital Set-Top Box Integrated Controllers DVB-CI (PCMCIA) Interface Timing SYSCLK Output BI_ADDRESS BI_DATA (output) VALID VALID VALID VALID Output Output BI_CS1 4 cycles BI_ADDRESS [14] (PCMCIA_iowr) BI_ADDRESS [15] (PCMCIA_iowr) BI_RW RMI_OE BI_DATA (input) (PCMCIA_we) (PCMCIA_oe) ] > t1 t2 4 cycles 3 cycles Output VALID t3 t4 Input BI_READY (PCMCIA_wait) Input Internal Signal 1 + TWT (If Ready is not used) TH (TH must be > 4 cycles) INT_cs (from EBIU) DVB-CI (PCMCIA) Interface Timing Values Symbol T1 T2 T3 T4 Input set-up time Input hold time Input set-up time Input hold time Parameter Min 5 3 15 2 Max Units ns ns ns ns Note 1. Refer to the SRAM timing diagram for DVB-CI output timing values on page (SRAM page). Note 2. BI_READY can also be configured as an asynchronous input. Audio Output Timing t1 DA_BIT_CLOCK DA_LR_CHANNEL_CLOCK, DA_SERIAL_DATA (0:2) t2 Output VALID Output t3 STB03_sds_041800.fm.01 April 18, 2000 Electrical Information Page 43 of 55 IBM39STB032XX IBM39STB034xx STB032xx and STB034xx Digital Set-Top Box Integrated Controllers Preliminary Audio Output Timing Values Symbol T1 8 T2 T3 Parameter DA_bit_clock period (1/[64 x 48 kHz]) Output valid time Output hold time 0 Min 326 18 Max Units ns ns ns IEEE 1284 Timings Compatibility Mode Handshake PData Valid Data nStrobe T1 T1 T1 Busy T1 T1 nAck T1 T1 T1 nSelectIn Compatibility Mode Handshake Timing Values Symbol T1 T2 T3 T4 T5 T6 T7 T8 Host Strobe Hold Ready Busy Reply Acknowledge (Ack) nBusy 0 500 ns 0 10 s Parameter Min 750 750 ns 750 0 500 500 s Max Units ns ns/s ns ns ns ns ns/s ns Electrical Information Page 44 of 55 STB03_sds_041800.fm.01 April 18, 2000 Preliminary IBM39STB032XX IBM39STB034xx STB032xx and STB034xx Digital Set-Top Box Integrated Controllers IEEE 1284 Mode Handshake Timing Values Symbol TH T TL TR TP TD Host response time Infinite response time Peripheral response time Peripheral response time (ECP mode only) Minimum setup or pulse width Minimum data setup time (ECP Modes only) Parameter Min 0 0 0 0 0.5 s 0 Max 1 Infinite 35 ms Units sec S Nibble Mode Handshake HostBusy (nAutoFd) PtrClk (nAck) nError Data Bit 0 Data Bit 4 Select Data Bit 1 Data Bit 5 PError Data Bit 2 Data Bit 6 Busy 1284 Active (nSelectIn) TP TL Data bit 3 Data bit 7 TH TL TL TL Note: See the table, "IEEE 1284 Mode Handshake Timing Values," for symbol values. STB03_sds_041800.fm.01 April 18, 2000 8 TH TP TH TP T Electrical Information Page 45 of 55 IBM39STB032XX IBM39STB034xx STB032xx and STB034xx Digital Set-Top Box Integrated Controllers Preliminary Byte Mode Handshake HostBusy (PPU_nAutoFd) HostClk (PPU_nStrobe) PtrClk (PPU_nAck) nDataAvail (PPU_nError) PData TP TH TL TL TP TH TP T TP TH TL TL TP 8 Ptr to Host Data available Ptr to Host Data not available Note: See the table, "IEEE 1284 Mode Handshake Timing Values," on page 45 for symbol values. ECP Forward Mode Handshake HostClk (nStrobe) PeriphAck (Busy) PData Byte 0 Byte 1 HostAck (nAutoFd) nCmd nCmd TD TR TH TL T TD T 8 Note: See the table, "IEEE 1284 Mode Handshake Timing Values," on page 45 for symbol values. Electrical Information 8 Page 46 of 55 STB03_sds_041800.fm.01 April 18, 2000 Preliminary IBM39STB032XX IBM39STB034xx STB032xx and STB034xx Digital Set-Top Box Integrated Controllers ECP Reverse Mode Handshake nAckReverse (PError) HostAck (nAutoFd) PeriphClk (nAck) PData Byte 0 Byte1 PeriphAck (Busy) nReverseRequest (nInit) TD T T 8 nCmd nCmd TL TH T TD T T 8 TL TH T 8 8 8 Note: See the table, "IEEE 1284 Mode Handshake Timing Values," on page 45 for symbol values. STB03_sds_041800.fm.01 April 18, 2000 8 Electrical Information Page 47 of 55 IBM39STB032XX IBM39STB034xx STB032xx and STB034xx Digital Set-Top Box Integrated Controllers Preliminary Negotiation Phase 1284 Active (PPU_nSelectIn) AckDataReq (PPU_PError) PData Extensibility Data Byte HostBusy (PPU_nAutoFd) HostClk (PPU_nStrobe) PtrClk (PPU_nAck) nDataAvail (PPU_nError) XFlag (Select) T TP TP TL TH TP TP TL T 8 Note: See the table, "IEEE 1284 Mode Handshake Timing Values," on page 45 for symbol values. IIC Timing Sys Clk 8 Output Output Output t1 IIC_SDA t1 IIC_SCL IIC Timing Values Symbol T1 Parameter Output valid time (falling edge) Min Max 15 Units ns Note: SDA and SCL outputs are open-drain. Electrical Information STB03_sds_041800.fm.01 April 18, 2000 Page 48 of 55 Preliminary IBM39STB032XX IBM39STB034xx STB032xx and STB034xx Digital Set-Top Box Integrated Controllers Smart Card (SCI) Timing SYSCLK t1 SC_CLK t2 SCn_IO Output Output SCI Timing Values t1 = (2 x SCCLK_CNT0) SYSCLK periods t2 = bit width = variable from 32 to 512 SC_clk periods = SCETU x SC_clk periods Note: SC_DETECT, SC_RESET, SC_SELECT, and SC_VCC_COMMAND are synchronous to the system clock and are not shown here. Modem Serial Interface Timing MODEM_CLK Input MODEM_CLK t1 t2 Input MODEM_RXD t1 t2 Input MODEM_FR t3 Input MODEM_TXD t4 t3 t1 Output MODEM_FR t4 Output Modem CODEC Timing Values Symbol T1 T2 T3 T4 Input setup time Input hold time Output hold time Output valid time Parameter Min 15 3 3 16 Max Units ns ns ns ns STB03_sds_041800.fm.01 April 18, 2000 Electrical Information Page 49 of 55 IBM39STB032XX IBM39STB034xx STB032xx and STB034xx Digital Set-Top Box Integrated Controllers Preliminary Note 1. MODEM_CLK can be configured to send and receive data on the rising or falling clock edge. Note 2. MODEM_FR can be an input or an output. Serial Control Port Timing Internal SYSCLK t2 SMC_CLK t3 SMC_TXD t5 SMC_RXD t6 t4 Output t1 Output Input SCP Timing Values Symbol T1 T2 T3 T4 T5 T6 SMC_clk period Output valid time Output valid time Output hold time Input setup time Input hold time 4 10 3 Parameter Min Max 80.8 12 13 Units ns ns ns ns ns ns Note: This timing diagram assumes the CI bit in the SCP SPMODE register is set to 0. If CI is set to 1, the LK signal is inverted. Electrical Information Page 50 of 55 STB03_sds_041800.fm.01 April 18, 2000 Preliminary IBM39STB032XX IBM39STB034xx STB032xx and STB034xx Digital Set-Top Box Integrated Controllers Additional Timing Information Interface Timing Information Compliant with Philips Semiconductors I2C Specification, dated 1995. Interface is asynchronous. Direct connect Compatible with ISO/IEC 7816-3. Interface is asynchronous. Direct connect. Functionally identical to National Semiconductor NS16450 in character mode (after reset). Interface is asynchronous. External transceiver logic is required. Functionally identical to IBM PowerPC403TM Serial Port Unit (SPU) (after reset). Compatible with the IrDA Specification 1.1 IrDA 1.0 SIR with data rates up to 115.2 Kbps IrDA 1.1 FIR with data rates up to 1.152 Mbps Interface is asynchronous External transceiver logic is required Inputs are asynchronous External DMA request inputs are asynchronous Capture timer inputs are asynchronous Interface is asynchronous Compatible with IBM RISCWatch probe Direct connect to probe Contact your IBM Applications Engineer for more information Compatible with IBM RISCTrace probe Direct connect to probe Contact your IBM Applications Engineer for more information IIC Smart Card (SC) Serial0/16550 Serial1/Infrared External Interrupts DMA GPT External Bus Master RISCWatch RISCTrace STB03_sds_041800.fm.01 April 18, 2000 Electrical Information Page 51 of 55 IBM39STB032XX IBM39STB034xx STB032xx and STB034xx Digital Set-Top Box Integrated Controllers Preliminary Mechanical Information Package Diagram Top of Package (BGA Side Down) Digital Set-Top Box Integrated Controller IBM P/N PowerPC(R) XXXXXXX ZZWWMMMM Date Code 0.25 C IBM39 STB03xxx xxx xxx OEM P/N 31 1.22 15.5 .610 1.27 .050 AC AB AA Y W V U T R P N M L K J H G F E D C B A 0 1 0 5 L 2 8 7 5 1 1 0 E 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 27.94 1.1 0. 20/. 008 B 0.15 C C A E52P SUBSTRATE .050 1.27 .610 15.5 GLOB TOP Mechanical Information Page 52 of 55 12.75 [0,502] 1.22 31 Cavity Cu STIFFENER 27.94 1.1 12.75 [0,502] (304X 0. 0.15 SOLDER BALL 0.30 0.10 MC MC A B Bottom of Package (BGA Side Up) STB03_sds_041800.fm.01 April 18, 2000 Preliminary IBM39STB032XX IBM39STB034xx STB032xx and STB034xx Digital Set-Top Box Integrated Controllers Development Support With IBM tools and the IBM PowerPC Embedded Tools Program, you receive the support you need to develop and debug your STB applications quickly. IBM Tools IBM offers Windows(R)95/98 - hosted development tools for STB applications that include: * STB and processor reference design and evaluation kits, including board, compiler, debugger, ROM source, schematics, etc. * RISCWatch debugger, with in-circuit, ROM monitor, RTOS-aware debugging and real-time non-invasive trace capability * Metaware High C/C++ compiler, highly optimized for the PowerPC processors Debug The STB03xxx facilitates development through its JTAG test access port. With IBM RISCWatch or other third-party debugger on a workstation, you can single-step the processor and interrogate the internal processor state. Additionally, the real-time debug port supports tracing the executed instruction stream out of the instruction cache. The trace status signals provide trace information in real-time instruction trace debug mode. This mode does not alter the performance of the processor. Third-Party Tool Support Through the IBM PowerPC Embedded Tools Program, you have access to hundreds of tools offered by over 75 industry-leading vendors. Often, the tools you currently use support PowerPC embedded processor products, such as the IBM STB010XX Digital Set-Top Box Integrated Controllers. For a list of the tools that are offered, visit IBM's tool support Web page at: http://www.chips.ibm.com/products/powerpc/tools/ Note: This document contains information on products in the sampling and/or initial production phases of development. This information is subject to change without notice. Verify with your IBM field applications engineer that you have the latest version of this document before finalizing a design. STB03_sds_041800.fm.01 April 18, 2000 Development Support Page 53 of 55 (R) Revision Log Revision March 24, 2000 March 31, 2000 April 11, 2000 April 18, 2000 Initial Release (revision 00). Update to GPIO table (revision 01). Update to Video Input Interface Timing diagram and table (revision 02). Various corrections to figures and tables (revision 03). Contents of Modification Preliminary Copyright and Disclaimer IBM39STB032XX IBM39STB034xx STB032xx and STB034xx Digital Set-Top Box Integrated Controllers (c) Copyright International Business Machines Corporation 2000. All Rights Reserved Printed in the United States of America February 2000 The following are trademarks of International Business Machines Corporation in the United States, or other countries, or both: IBM IBM Logo CoreConnect PowerPC logo PowerPC 405 Dolby is a trademark of Dolby Laboratories. Java and all Java-based trademarks and logos are trademarks or registered trademarks of Sun Microsystems, Inc. in the United States and/or other countries. Windows is a trademark of Microsoft Corporation in the United States and/or other countries. Other company, product, and service names may be trademarks or service marks of others. All information contained in this document is subject to change without notice. The products described in this document are NOT intended for use in implantation or other life support applications where malfunction may result in injury or death to persons. The information contained in this document does not affect or change IBM's product specifications or warranties. Nothing in this document shall operate as an express or implied license or indemnity under the intellectual property rights of IBM or third parties. All information contained in this document was obtained in specific environments, and is presented as an illustration. The results obtained in other operating environments may vary. Product name is subject to change. While the information contained herein is believed to be accurate, such information is preliminary, and should not be relied upon for accuracy or completeness, and no representations or warranties of accuracy or completeness are made. THE INFORMATION CONTAINED IN THIS DOCUMENT IS PROVIDED ON AN "AS IS" BASIS. In no event will IBM be liable for damages arising directly or indirectly from any use of the information contained in this document. IBM Microelectronics Division 1580 Route 52, Bldg. 504 Hopewell Junction, NY 12533-6351 The IBM home page can be found at http://www.ibm.com The IBM Microelectronics Division home page can be found at http://www.chips.ibm.com STB03_sds_041800.fm.01 April 18, 2000 STB03_sds_041800.fm.01 April 18, 2000 Revision Log Page 55 of 55 |
Price & Availability of IBM39STB032XX
 |
|
|
|
|
All Rights Reserved © IC-ON-LINE 2003 - 2022 |
| [Add Bookmark] [Contact Us] [Link exchange] [Privacy policy] |
|
Mirror Sites : [www.datasheet.hk]
[www.maxim4u.com] [www.ic-on-line.cn]
[www.ic-on-line.com] [www.ic-on-line.net]
[www.alldatasheet.com.cn]
[www.gdcy.com]
[www.gdcy.net] |